The present invention relates to a semiconductor package, and more particularly, to a semiconductor package in which passive elements are embedded, and a method for manufacturing the same.
In the semiconductor industry, a semiconductor package is a structure in which a semiconductor chip, having a fine circuit pattern designed therein, is molded by resin, ceramic, etc. so that the semiconductor chip can be protected from the surrounding environment and can be mounted to an electronic appliance. Rather than packaging a semiconductor chip in order to simply protect the semiconductor chip and then mounting the semiconductor chip to an electronic appliance, a semiconductor chip may be packaged in order to improve the performance and quality of an electronic appliance, and also to take advantage of the miniaturization and multi-functionality of the electronic appliance.
Semiconductor packaging technology has been continuously developed in order to meet the demands toward the miniaturization and multi-functionality of an electronic appliance. For example, the demand toward miniaturization is followed by the development of a chip-size package which has a size approaching the size of a chip, and the demand toward multi-functionality is followed by the development of a stack package in which a plurality of chips capable of performing various functions are stacked upon one another. The research for the chip-size package and the stack package have actively been conducted in a variety of ways in terms of structure and method.
However, in spite of efforts to decrease the size and the thickness of a semiconductor package to attain miniaturization of the semiconductor package, due to the presence of passive elements such as a resistor, an inductor and a capacitor, which are mounted along with the semiconductor package, limitations necessarily exist in decreasing the size and the thickness of the printed circuit board which is finally arranged in an electronic appliance, and this serves as a factor impeding the miniaturization and the slimness of the electronic appliance.
Also, due to the fact that the passive elements are mounted to the printed circuit board as in the conventional art, electrical connection lengths between the semiconductor package and the passive elements are long. As a consequence, since the inductance component increases, limitations exist in improving the electrical performance of the electronic appliance.
In addition, in the case of a wafer level package which is a kind of chip-size package, as the rear surface of a semiconductor chip is exposed to the outside, the semiconductor chip is likely to be damaged by an external shock and mis-operate, whereby it is difficult to ensure the reliability of an end product.